1. Field of the Invention
The present invention relates to a voltage reference circuit which is basically employed in an analog integrated circuit and is an indispensable circuit of an A/D converter or a D/A converter, more particularly to a voltage reference circuit employing a capacitor and an operational amplifier (OP AMP) for preventing deterioration of an output reference voltage due to the change of time and temperature upon integration thereof.
2. Description of the Prior Art
An arrangement of a conventional bandgap reference circuit is shown in FIG. 1. In the figure, a voltage reference circuit comprises a plurality of resistors R.sub.1, R.sub.2 and R.sub.3, a plurality of transistors Q.sub.1 and Q.sub.2, V.sub.OS, and an OP AMP.
The transistors Q.sub.1 and Q.sub.2 are substrate p-n-p transistors whose collectors are always tied to the most negative power supply. The OP AMP is a CMOS operational amplifier. FIG. 2A is a side view of the transistor shown in FIG. 1.
All resistors are p.sup.+ -diffusion registers in the n.sup.- -well, and the CMOS operational amplifier is assumed to have an infinite gain with an offset voltage of V.sub.OS. This assumption is justified because CMOS OP amps usually have enough gains such that the error due to finite -gain effects is negligible in this application. If we assume that transistor Q.sub.1 has an area that is larger, by a factor A, than transistor Q.sub.2, and both are in the forward active region, then output voltage V.sub.REF is given by, ##EQU1## where V.sub.BE is an emitter-base voltage of the transistor Q.sub.1, .DELTA.V.sub.BE is the difference between emitter-base voltages of the transistors Q.sub.1 and Q.sub.2, and V.sub.OS is the input offset voltage of the OP AMP.
The value of this expression is influenced by the nonideal properties of the bipolar transistors shown in FIG. 2B. The emitter-base voltage of the transistor Q.sub.1 is given by, ##EQU2## where V.sub.T is the thermal voltage ##EQU3## I.sub.1 is the emitter current of transistor Q.sub.1, I.sub.S1 is the saturation current of transistor Q.sub.1, .beta..sub.1 is a current gain of transistor Q.sub.1 and .gamma..sub.b is the effective series base resistance of Q.sub.2.
In Eq. 2, the second term results from the fact that while the collector current is a well-defined function of the emitter-base voltage, the current sensed and controlled by this circuit is the emitter current, and the third term results from the voltage drop in the finite series base resistance. The difference between the two emitter-base voltages is given by ##EQU4## where I.sub.2 is the emitter current of transistor Q.sub.2 and .beta..sub.2 is the current gain of transistor Q.sub.2.
If the bipolar transistor used to implement the reference are ideal in the sense that they have infinite current gain and zero base resistance, and if the emitter currents of the transistors are in fact equal than only the first terms in E.sub.qs. 2 and 3 are nonzero.
However, because of the relatively poor performance of CMOS-compatible devices, these terms can strongly influence the performance of the reference.
The presence of the operational amplifier offset voltage in the output, multiplied by the gain factor ##EQU5## which is typically on the order of 10, is also an important degradation.
Also, the variation of the bias current I.sub.1 and I.sub.2 with temperature must be carefully considered. The offset of the OP AMP is the biggest error source that causes the nonreproducibility in the output voltage temperature coefficient.
A bandgap reference is trimmed to an output voltage which is predetermined to give a near-zero temperature coefficient of the output.
If we assume the offset voltage V.sub.OS is independent of temperature, the resulting temperature coefficient error due to a 5 mV V.sub.OS, is expressed by the equation, ##EQU6##
As mentioned above, when the input offset voltage changes in accordance with temperature, the reference output voltage V.sub.REF also changes in accordance with temperature, the reference, and the offset voltage of the circuit integrated by a MOS process is higher than that of the circuit integrated by a bipolar process, which exert a harmful influence upon the circuit.
On the other hand, in the conventional NMOS voltage reference circuit shown in FIG. 3, the transistors Q.sub.1 and Q.sub.2 are connected to two input terminals of the OP AMP. The transistor connected to the non-inverting terminal is a depletion type, and the transistor connected to the inverting terminal is an enhancement type. The reference voltage V.sub.REF is generated from a gate-source voltage difference of two N-channel MOSFETs.
The transistors are an enhancement device and a depletion device. The transistors also have the offset voltage regulated by the ion implantation, and two MOSFETs are biased under the saturation current condition.
At this time, as the major change of the reference voltage circuit is occured by the change of the offset voltage with respect to temperature. The reference voltage V.sub.REF is determined by threshold voltage of two transistors.
However, because it is difficult to correctly control the threshold voltage on integration, the problem which the reference voltage V.sub.REF can't be correctly controlled is occured.